luna_soc.gateware.core.blockram module

class luna_soc.gateware.core.blockram.Peripheral(*args, src_loc_at=0, **kwargs)[source]

Bases: Component

SRAM storage peripheral.

Parameters

sizeint: Memory size in bytes.
data_widthint: The width of each memory word.
granularityint: The number of bits of data per each address.
writablebool: Memory is writable.
initlist[byte] Optional: The initial value of the relevant memory.
namestr: A descriptive name for the given memory.

Attributes

busamaranth_soc.wishbone.Interface: Wishbone bus interface.

property constant_map

elaborate(platform)[source]

property init