luna_soc.gateware.cpu.vexriscv module

class luna_soc.gateware.cpu.vexriscv.VexRiscv(*args, src_loc_at=0, **kwargs)

Bases: Component

arch = 'riscv'

byteorder = 'little'

data_width = 32

elaborate(platform)

name = 'vexriscv'

property reset_addr