luna_soc.generate.introspect module

Introspection tools for SoC designs.

luna_soc.generate.introspect.csr_base(memory_map: MemoryMap) → int

Scan a memory map for the starting address for csr peripheral registers.

luna_soc.generate.introspect.csr_peripherals(memory_map: MemoryMap) → dict[Name, list[ResourceInfo]]

Scan a memory map for csr peripheral registers.

luna_soc.generate.introspect.interrupts(fragment: Component) → dict[int, (<class 'str'>, <class 'amaranth.lib.wiring.Component'>)]

luna_soc.generate.introspect.memory_map(fragment: Component) → MemoryMap

luna_soc.generate.introspect.reset_addr(fragment: Component) → MemoryMap

luna_soc.generate.introspect.soc(fragment: Component) → Component

luna_soc.generate.introspect.wb_peripherals(memory_map: MemoryMap) → dict[~amaranth_soc.memory.MemoryMap.Name, list[tuple[~amaranth.lib.wiring.Component, ~amaranth_soc.memory.MemoryMap.Name, (<class 'int'>, <class 'int'>)]]]

Scan a memory map for wishbone peripherals.