luna_soc.gateware.cpu.minerva module

class luna_soc.gateware.cpu.minerva.Minerva(*args, src_loc_at=0, **kwargs)

Bases: Component

arch = 'riscv'

byteorder = 'little'

data_width = 32

elaborate(platform)

property muldiv

name = 'minerva'

property reset_addr